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MY PUBLICATIONS

Currently, my work focuses on Semiconductor Device Modelling and Design. This area of topic can be classified from the well known devices like Laptops, mobiles, displays, etc. The heart of such modules is none other than a component called "Transistor". Because, it is a decider of device performance in terms of speed, power consumption and dissipation, and many more. Hence, we invent and model such novel transistors for the future technologies and the requirements.

2024:

1. Y.-Z. Chen, N. Thoti, and Y.-T. E. Tang, "Study of Spacing-induced Fringing Effects on Emerging CFET Technology Nodes," 2024 IEEE Silicon Nanoelectronics Workshop, USA (accepted).

2023

  1. N. Thoti and Y. Li, “Design and exploration of vertically stacked complementary tunneling FETs", Applied Physics Express (APEX), vol. 17, p. 014001, 2023 (IF:2.3).

  2. N. Thoti and Y. Li, “DC and AC characteristics of Si/SiGe based vertically stacked complementary-tunneling FETs,” Nanotechnology, vol. 34, no. 50, p. 505208, 2023 (IF:3.5).​

2022:​

  1. C. Akbar, Y. Li, and N. Thoti, "Device-Simulation-Based Machine Learning Technique for the Characteristic of Line Tunnel Field-Effect Transistors, IEEE Access, vol. 10, pp. 53098–53107, 2022 (IF: 3.9).

  2. N. Thoti, and Y. Li “Design of GAA Nanosheet Ferroelectric Area Tunneling FET and Its Significance with DC/RF Characteristics Including Linearity Analyses”, Nanoscale Research Letters, Vol.17, no. 53, pp. 1–11, 2022 (IF:6.5).

  3. N. Thoti, Y. Li, W. L. Sung “Significance of Work Function Fluctuations in SiGe/Si Hetero-Nanosheet Tunnel-FET at Sub-3 nm Nodes”, IEEE Transactions on Electron Devices, vol. 69, no. 1, pp. 434–438, 2022, (IF:3.1).

  4. N. Thoti and Y. Li, “Gate‐all‐around nanowire vertical tunneling FETs by ferroelectric internal voltage amplification,” Nanotechnology, vol. 33, no. 5, p. 055201, 2022 (IF:3.5).

2021:​

  1. N. Thoti, Y. Li, “An Optimized ferroelectric option to Nanosheet Vertical Tunneling FETs”, International Electron Devices & Materials Symposium  (IEDMS), Taiwan, (18-19, November 2021).

  2. N. Thoti and Y. Li, "Ample Utilization of Polarization and Coercive Fields with Metal-Ferroelectric Options in Tunnel FETs", Symposium on Nano-Device Circuits and Technology (SNDCT), Hsinchu-Taiwan, 20-21 May, 2021.

  3. N. Thoti and Y. Li, “Promised design of energy‐efficient negative capacitance vertical tunneling FET”, ECS Journal of Solid State Science and Technology, vol. 10, no. 7, pp. 075002, 2021 (IF: 2.2).

  4. N. Thoti and Y. Li, “p‐SiGe nanosheet line tunnel field‐effect transistors with ample exploitation of ferroelectric”, Japanese Journal of Applied Physics, vol. 60, no. 5, pp. 054001-1–5, 2021 (IF: 1.5).

  5. N. Thoti and Y. Li, “A Novel Design of Ferroelectric Nanowire Tunnel Field Effect Transistors”, International Symposium on VLSI-TSA, Taiwan, 2021, pp. 74–75.

  6. C. Akbar, N. Thoti, and Y. Li, “Machine Learning Approach to Predicting Tunnel Field-Effect Transistors”, International Symposium on VLSI-TSA, Taiwan, 2021, pp. 70–71.

2020:

  1. N. Thoti and Y. Li, “Energy Efficient Ferroelectric Tunneling Field Effect Transistors”, India International Science Festival/ Young Scientist’s conference”, CSIR, India Dec. 2020.

  2. N. Thoti and Y. Li, Influence of Fringing-Field on DC/AC Characteristics of Si1-xGex based Multi-Channel Tunnel FETs, IEEE Access, vol. 8, pp. 208658–208668, 2020 (IF: 3.9).

  3. N. Thoti, Y. Li, S.R. kola, S. Samukawa, Introducing Strained SiGe based Negative Capacitance Line-Tunneling Field Effect Transistors, International Electron Devices & Materials Symposium (IEDMS), Taiwan, Oct. 2020.

  4. S.R. kola, Y. Li, N. Thoti, “Characteristics of H0.5Z0.5O2 Negative Capacitance MFMIS and MFIS NCFETs and Random Telegraph Noise Induced by Single Charge Trap”, International Electron Devices & Materials Symposium  (IEDMS), Taiwan,(October 2020).

  5. S. R. kola, Y. Li, N. Thoti, Characteristics of Gate-All-Around Silicon Nanowire and Nanosheet MOSFETs with Various Spacers, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Japan, IEEE Xplore (October 2020).

  6. N. Thoti, Y. Li, S.R. kola, S. Samukawa “High-Performance Metal-Ferroelectric-Semiconductor Nanosheet Line Tunneling Field Effect Transistors with Strained SiGe” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Japan, IEEE Xplore (October 2020).

  7. N. Thoti, Y. Li, S.R. kola, S. Samukawa, Modelling and Simulations of Highly-Efficient Metal-Ferroelectric-Nanosheet Line-Tunnel FETs for Sub-5-nm Technology Nodes, International Conference on Solid State Devices and Materials (SSDM), Japan (September 2020).

  8. N. Thoti, Y. Li, S. Kola, “Scaling limitations of line TFETs at Sub-8-nm Technology Node”, 2020 International Symposium on VLSI-TSA, Taiwan (August 2020).

  9. N. Thoti, Y. Li, S. Kola, “New Proficient Ferroelectric Nanosheet Line Tunneling FETs with Strained SiGe through Scaled n-epitaxial Layer”, IEEE International Conference on Nanotechnology (IEEE NANO),  Canada, IEEE Xplore, (July 2020).

  10. S.R. kola, Y. Li, N. Thoti, “Effects of Spacer and Single-Charge Trap on Voltage Transfer Characteristics of Gate-All-Around Silicon Nanowire CMOS Devices and Circuits",  IEEE International Conference on Nanotechnology (IEEE NANO),  Canada, IEEE Xplore (July 2020).

  11. N. Thoti, Y. Li, S. Kola, S. Samukawa, “Optimal Inter-Gate Separation and Overlapped Source of Multi-Channel Line Tunnel FETs”, IEEE Open Journal of Nanotechnology, vol. 1, pp. 38-46, 2020 (IF: 1.7).

  12. S. Kola, Y. Li, N. Thoti, “Random telegraph noise in gate-all-around silicon nanowire MOSFETs induced by a single charge trap or random interface traps”,  Journal of Computational Electronics, Springer, vol. 19, no. 1, pp. 253–262, 2020 (IF: 2.1).

  13. S. Kola, Y. Li, N. Thoti, “Effects of Dual Spacer on Electrical Characteristics and Random Telegraph Noise of Gate-All-Around Silicon Nanowire p-Type Metal-Oxide-Semiconductor Field-Effect-Transistors“, Japanese Journal of Applied Physics, IOPScience, vol. 59, no. SG, pp. SGGA02-1–5, 2020 (IF: 1.5).

​

2019:

  1. N. Thoti, Y. Li, S. Kola, “Scaling and short channel effects in Multi-channel Tunnel FETs”, XXth International Workshop on Physics of Semiconductor Devices (IWPSD), India (2019).

  2. S. Kola, Y. Li, N. Thoti, “Spacer Effect on Random Telegraph Noise of Gate-All-Around Silicon Nanowire n-MOSFETs for Sub-7-nm Technological Nodes”, XXth International Workshop on Physics of Semiconductor Devices (IWPSD), India (2019).

  3. N. Thoti, Y. Li, S. Kola, “Electrical Characteristic of Multi-Channel Strained Si1-xGex TFETs”, International Electron Devices & Symposium (IEDMS), Taiwan (2019).

  4. S. Kola, Y. Li, N. Thoti, “Random Telegraph Noise Induced by Single-Charge Trap of Gate-All-Around Silicon Nanowire MOSFETs with Spacer”, International Electron Devices & Symposium (IEDMS), Taiwan, 2019.

  5. S. R. Kola, Y. Li, N. Thoti, C.-Y. Chen, W.-L. Sung, “Characteristic Variability and Random Telegraph Noise of Gate-All-Around Silicon Nanowire MOSFETs with Asymmetric Dual Spacer Induced by Single Charge Trap, International Conference on Solid State Devices and Materials (SSDM), Japan, (September 2019), pp. 633-634.

  6. N. Thoti, G. Anitha, G. Dilli Rani, R. Haritha, A. Kishore, “Ultra scaled Multi-channel TFET design and characterization for its optimized performance at 10 nm regime”, 5th International Conference on Nano science and Nanotechnology, SRM University, India, 2019.

 

2018:

  1. N. Thoti, “Performance metrics estimation in IC process flow by using TCAD simulations,” TEPEXI Scientific Bulletin, Mexico, vol. 5, no. 10, 2018.

  2. N. Thoti, R. Haritha, and M. Nandini, “Investigation of optimized Si1-x Gex 3D-fin-TFET by varying the fin height,” IEEE International Conference on Electrical, Control & Communication (RTECC’18), IEEE xplore, pp. 45–49, 2018.

  3. N. Thoti, R. Haritha, A. Kishore, A. Rajasekhar, and V. Narasimha, “Comparative investigation of Si/Si0.6Ge0.4/InAs 3D-fin-TFET for its optimized performance,” IEEE Fourth International Conference on Devices, Circuits and Systems (ICDCS’18), IEEE Xplore, pp. 189–193, 2018.

 

2017:

  1. N. Thoti and R. Haritha, “Under-lapped DGTFET design and characterization with high-k dielectrics,” in 1st International Conference on Advanced Technologies in Engineering, Management and Sciences - ICATEMS’17, pp. 47–50, 2017.

  2. N. Thoti and B. Lakshmi, “RF performance enhancement in multi- fin TFETs by scaling inter fin separation,” Materials Science in Semiconductor Processing, Elsevier, vol. 71, pp. 304–309, 2017 (IF: 4.1).

  3. N. Thoti and B. Lakshmi, “Design and Optimization of Multi-fin TFETs using TCAD Simulations,” in Second National Conference on Recent Developments in Electronics, University of Delhi, vol. 1, pp. 62–66, 2017.

 

2013 and beyond:

  1. S. Chitra and N. Thoti, “Implementation of Video Steganography Using Hash Function in LSB Technique,” International Journal of Engineering Research & Technology (IJERT), vol. 2, no. 11, pp. 3396–3403, 2013.

  2. L. Hari hara bramha and N. Thoti, “Face Recognition System Using DCT Pyramid Method,” in National conference on Emerging Trends in Electronics and Communication Technology, JNTU Anantapuramu, pp. 121–129, 2012.

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